VLSI ReferencePoint Suite
The VLSI ReferencePoint Suite is an exclusive, growing series of high-impact, in-depth articles inspired by our users.
TABLE OF CONTENTS VLSI ReferencePoint Suite
Point 2: Behavioral Modeling Using Verilog
Abhiram Mishra
Behavioral modeling is an abstraction level of Verilog Hardware Description Language (HDL) that you use to simulate hardware without considering the actual hardware components to be used. You can use this abstraction to describe the behavior of the hardware in algorithms. For example, you can use Verilog to describe a decoder in terms of an algorithm instead of gates.
This ReferencePoint describes behavioral modeling using Verilog HDL. It also explains the procedural constructs, timing controls, block statement, procedural assignments, conditional statement, case statement, loop statement, and procedural continuous assignments in Verilog.
The Abstraction Levels for Modeling
You use Verilog to design hardware at four abstraction levels:
-
Switch
-
Gate
-
Data flow
-
Behavioral
Switch Level
The switch level is the basic abstraction level of hardware design in Verilog and is used the least in modeling circuits. This level is not appropriate if you work with big and complex designs. At this level, the circuit is described in terms of transistors, such as negative metal oxide semiconductor (nMOS) and positive metal oxide semiconductor (pMOS). You can also describe the circuit in terms of other transistors, such as complementary metal oxide semiconductors (cMOS), resistive complementary metal oxide semiconductors (rcMOS), and resistive n-type metal oxide semiconductors (rnMOS).
Listing 2-2-1 shows the switch level description of an and gate:
Listing 2-2-1: Switch Level Description of an and Gate
// Code showing gate level description of 4 by1 multiplexermodule by1mux (Out, I0,I1,I2,I3, S0,S1);// Declaration Statement// Input to the Circuit// S0 and S1 represent the Select...
Copyright SkillSoft Corporation 2002 under license agreement with Books24x7
