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TABLE OF CONTENTS VLSI ReferencePoint Suite
Point 3: Structural Modeling Using Verilog
Abhiram Mishra
Structural modeling describes the interconnection between the components of a hardware module and the design of the hardware by connecting various modules and gates, such as and and or.
This ReferencePoint discusses structural modeling using Verilog HDL, gate instantiation, and User-Defined Primitives (UDP) instantiation.
Basics of Structural Modeling
You can define the structural model of a hardware module using four techniques: gate instantiation, switch instantiation, UDP instantiation, and module instantiation. For example, the structural model of an xor gate describes the interconnection between various nand gates. Figure 2-3-1 shows the gate-level description of an xor gate:
Figure 2-3-1: Gate Level Description of an Xor Gate
Listing 2-3-1 shows the structural description of an xor gate:
Listing 2-3-1: Structural Description of an Xor Gate
// Structural Description of an xor Gate// A and B are inputs to the xor Gate// Out is the output from the xor Gate// ABbar is the connecting wire in the xor Gate// I1 and I2 are the Connecting Wires in the xor Gate// Module Instantiation Beginsmodule xorgate(Out, A,B);// Declaration Statementsoutput Out;input A, B;wire ABbar;// Generates an Intermediate Output ABbar// the First Parameter in the Bracket is the Output// the Other Parameters are Inputsnand N1(ABbar, A,B);nand N2 ( I1, ABbar, A);nand N3 (I2, ABbar, B);//The Output Gatenand N4 ( Out, I1,I2);endmodule// End of the Sample Structure Module
The above code describes the structural model of an xor gate. This code instantiates the nand gates and connects them through wires. You instantiate the nand gate N1...
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