VLSI ReferencePoint Suite
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Point 4: Introducing Verilog HDL Synthesis
Abhiram Mishra
You use a high-level Hardware Description Language (HDL) such as Verilog to describe a circuit. Synthesis is a process of converting the circuit description written in HDL to a gate-level netlist or data flows between the output and input ports. A gate-level netlist describes the connection among the various pins of the gate.
Synthesis tools support the synthesis of high-level language constructs such as for and if loops. These tools also enable you to describe the design in terms of gate-level netlists. Synthesis tools provide engines to optimize circuits and consider various constraints. Constraints are declarations that define the goal of the circuit design such as area, delay, and power.
This ReferencePoint explains the process of synthesis and the process of constraining a design for synthesis. It also describes the HDL code that can be synthesized and the equivalent hardware of Verilog constructs.
Overview of HDL Synthesis
The HDL synthesis process requires the use of synthesis tools to convert the HDL description of a circuit into a gate-level netlist. Synthesis tools take as input the description of the circuit written in HDL, the constraints under which the circuit has to perform, and a technology library. A technology library is a set of cells and macros available in a particular technology. This set may contain simple cells, such as and, or, nand, and nor gates, simple flip-flops, and macros, such as multiplexers and adders. Synthesis tools use only these cells to realize the circuit.
HDLs and their conversion to...
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