VLSI ReferencePoint Suite
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TABLE OF CONTENTS VLSI ReferencePoint Suite
List of Examples
Verilog Hardware Description Language
Point 1: Introducing Verilog HDL
- Listing 2-1-1: Sample Data Flow Model of Master Slave SR Flip Flop
- Listing 2-1-2: A Sample Structural Model
- Listing 2-1-3: Module Description of a 4-Bit Adder
- Listing 2-1-4: A 3X8 Decoder
- Listing 2-1-5: A 15-Bit Register
- Listing 2-1-6: A 10-Bit Shift Register
- Listing 2-1-7: A Universal Register
- Listing 2-1-8: A 15-Bit Up Down Counter
- Listing 2-1-9: A 4-State Moore Machine
- Listing 2-1-10: A Sample Mealy Machine
- Listing 2-1-11: Describing an ALU
- Listing 2-1-12: A Sample UDP
- Listing 2-1-13: A Sequential UDP
- Listing 2-1-14: A Combinational UDP
Point 2: Behavioral Modeling Using Verilog
- Listing 2-2-1: Switch Level Description of an and Gate
- Listing 2-2-2: A 4X1 Multiplexer
- Listing 2-2-3: The 4X1 Multiplexer Data Flow Design
- Listing 2-2-4: Behavioral Model of a 4X1 Multiplexer
- Listing 2-2-5: A Sample Design Containing Three Levels of Abstraction
- Listing 2-2-6: A Module Containing the initial Block
- Listing 2-2-7: Multiple Initial Blocks in the Module
- Listing 2-2-8: A Clock Generator with a Period of 20 Units of Time and 50% Duty Cycle
- Listing 2-2-9: The Use of the always and initial Blocks
- Listing 2-2-10: Use of the Blocking Statement in Behavioral Modeling
- Listing 2-2-11: Use of Nonblocking Statements in a Module
- Listing 2-2-12: Nonblocking Assignment Statements Inside a Module
- Listing 2-2-13: Using Blocking and Nonblocking Statements in the Same Block
- Listing 2-2-14: Timing Delay
- Listing 2-2-15: Use of Event-Based Triggering
- Listing 2-2-16: Event Triggering
- Listing 2-2-17: Using the wait Statement
- Listing 2-2-18: Using the if-else Statements
- Listing 2-2-19:...
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