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Parity checkers are integrated circuits (ICs) used in digital systems to detect errors when streams of bits are sent from a transmitter to a receiver. Parity generators calculate the parity of data packets and add a parity amount to them. Both parity checkers and generators use parity memory, a basic form of error detection which provides an extra bit for every byte stored. Whenever a byte is written to memory, the parity circuit examines the byte and determines whether it contains an even or odd number of ones. If the data byte contains an even number of ones, the extra (parity) bit is set to 1; otherwise, the parity bit is set to 0. When the data is read back from memory, the parity circuit examines all of the bits and determines if there are an odd or even number of ones. An even number of ones indicates that there is an error in one of the bits because a parity circuit, when storing a byte, always sets an error-free parity bit to indicate an odd number of ones. When a parity error is detected, the parity circuit generates a non-maskable interrupt (NPI) that halts the processor, ensuring that the error does not corrupt other data.

Performance Specifications

There are several important performance specifications for parity checkers and generators. Number of bits is the number of words that devices can handle in parallel. Common configurations are 4, 5, 6, 8, 9, 12, or 16 bits. Supply voltages for parity checkers and generators range from - 5 V to 5 V and include intermediate voltages such as - 4.5 V, - 3.3 V, - 3 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, and 3.6 V. Propagation delay is the time interval between the occurrence of a change at the output and the application of a change at the inputs. Operating temperature is a full-required range.

Selecting Parity Checkers and Generators

Selecting parity checkers and generators requires an analysis of logic families. Transistor-transistor logic (TTL) and related technologies such as Fairchild advanced Schottky TTL (FAST) use transistors as digital switches. By contrast, emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions. Another logic family, complementary metal-oxide semiconductor (CMOS), uses a combination of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. Bipolar CMOS (BiCMOS) is a silicon-germanium technology that combines the high speed of bipolar TTL with the low power consumption of CMOS. Other logic families for parity checkers and generators include cross-bar switch technology (CBT), gallium arsenide (GaAs), integrated injection logic (I2L) and silicon on sapphire (SOS). Gunning with transceiver logic (GTL) and gunning with transceiver logic plus (GTLP) are also available.


Parity checkers and generators are available in a variety of IC package types and with different numbers of pins. Basic IC package types for ALUs include ball grid array (BGA), quad flat package (QFP), single in-line package (SIP), and dual in-line package (DIP). Many packaging variants are available. For example, BGA variants include plastic-ball grid array (PBGA) and tape-ball grid array (TBGA). QFP variants include low-profile quad flat package (LQFP) and thin quad flat package (TQFP). DIPs are available in either ceramic (CDIP) or plastic (PDIP). Other IC package types include small outline package (SOP), thin small outline package (TSOP), and shrink small outline package (SSOP).