Field-Programmable Gate Arrays (FPGA) Information
Field-programmable gate arrays (FPGAs) are integrated circuits (ICs) that contain an array of logic cells surrounded by programmable I/O blocks. FPGAs contain as many as tens of thousands of logic cells and an even greater number of flip-flops. Because of cost, field-programmable gate arrays do not provide a 100% interconnection between logic cells; however, FPGAs still provide significantly higher capacities than programmable logic devices (PLDs) that are interconnected through a central global routing pool.
Design engineers use field-programmable gate arrays to program electrical connections through several iterations in order to minimize non-recurring costs. FPGAs are used in applications ranging from data processing and storage, to instrumentation, telecommunications, and digital signal processing. Other terms for FPGA include logic cell array (LCAs) and programmable application-specific integrated chip (pASIC).
Field-programmable gate arrays are available with different numbers of system gates, shift registers, logic cells, and look up tables. Logic blocks or logic cells (LCs) do not include I/O blocks, but generally contain a look up table to generate any function of inputs, a clocked latch (flip-flop) to provide registered outputs, and control logic circuits for configuration purposes. Logic cells are also known as logic array blocks (LABs), logic elements (LEs) and configurable logic blocks (CLBs). Look up tables (LUTs) or truth tables are used to implement a single logic function by storing the correct output logic state in a memory location that corresponds to each particular combination of input variables.
Selecting field-programmable gate arrays requires an analysis of memory, performance, and I/O interface requirements. Available memory types include:
- Content addressable memory (CAM)
- Flash, random access memory (RAM)
- Dual-port RAM
- Read-only memory (ROM)
- Electrically erasable programmable read-only memory (EEPROM)
- First-in, first-out (FIFO)
- Last-in, first out (LIFO)
Performance considerations include internal frequency, the number of integrated phase-locked loops (PLLs) and delay-locked loops (DLLs) with clock-frequency-synthesis capabilities, and the total number of I/O ports. I/O interfaces for field-programmable gate arrays include accelerated graphics port (AGP), bus low voltage differential signaling (BLVDS), and peripheral component interconnect (PCI).
Field-Programmable Gate Arrays Options
Field-programmable gate arrays are available with many logic families. Transistor-transistor logic (TTL) and related technologies such as Fairchild advanced Schottky TTL (FAST) use transistors as digital switches. By contrast, emitter coupled logic (ECL) uses transistors to steer current through gates that compute logical functions. Another logic family, complementary metal-oxide semiconductor (CMOS), uses a combination of P-type and N-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. Logic families for field-programmable gate arrays include:
- Crossbar switch technology (CBT)
- Gallium arsenide (GaAs)
- Integrated injection logic (I2L)
- Silicon on sapphire (SOS)
Gunning with transceiver logic (GTL) and gunning with transceiver logic plus (GTLP) for field-programmable gate arrays are also available.
Field-programmable gate arrays are available in a variety of IC package types and with different numbers of pins and flip-flops. Basic IC package types for field-programmable gate arrays include:
- Ball grid array (BGA)
- Quad flat package (QFP)
- Single in-line package (SIP)
- Dual in-line package (DIP)
Many packaging variants are available. For example, BGA variants include plastic-ball grid array (PBGA) and tape-ball grid array (TBGA). QFP variants include low-profile quad flat package (LQFP) and thin quad flat package (TQFP). DIPs are available in either ceramic (CDIP) or plastic (PDIP). Other IC package types for field-programmable gate arrays include small outline package (SOP), thin small outline package (TSOP), and shrink small outline package (SSOP).
JEDEC JESD 12 -- Standard for Gate Array Benchmark Set
JEDEC JESD 12-3 -- CMOS Gate Array Macrocell Standard