Real Time Systems Design And Analysis

Chapter 7.2.2 - Analysis of Polled Loops

7.2.2   Analysis of Polled Loops

The response-time delay for a polled loop system consists of three components:
the hardware delays involved in setting the software flag by some external device;
the time for the polled loop to test the flag; and the time needed to process the
event associated with the flag (Figure 7.4). The first delay is on the order of
nanoseconds and can be ignored. The time to check the flag and jump to the
handler routine can be several microseconds. The time to process the event related
to the flag depends on the process involved. Hence, calculation of response time
for polled loops is quite easy.

The preceding case assumes that sufficient processing time is afforded between
events. However, if events begin to overlap, that is, if a new event is initiated
while a previous event is still being processed, then the response time is worse. In
general, if f is the time needed to check the flag and P is the time to process the
event, including resetting the flag (and ignoring the time needed by the external
device to set the flag), then the response time for the nth overlapping event is
bounded by

 

Typically, some limit is placed on n, that is, the number of events that can
overlap. Two overlapping events may not be desirable in any case.

7.2.3   Analysis of Coroutines

The absence of interrupts in a coroutine system makes the determination of
response time rather easy. In this case, response time is simply found by tracing
the worst-case path through each of the tasks (Figure 7.5). In this case, the execution
time of each phase must be determined, which has already been discussed.

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