Real Time Systems Design And Analysis

Chapter 7.2.8 - Deterministic Performance

7.2.8   Deterministic Performance

Cache, pipelines, and DMA, all designed to improve average real-time performance,
destroy determinism and thus make prediction of real-time performance
troublesome. In the case of cache, for example, is the instruction in the cache?
From where it is being fetched has a significant effect on the execution time of
that instruction. To do a worst-case performance, it must be assumed that every
instruction is not fetched from cache but from in memory. However, to bring
that instruction into the cache, costly replacement algorithms must be applied.
This has a very deleterious effect on the predicted performance. Similarly, in the
case of pipelines, one must always assume that at every possible opportunity the
pipeline needs to be flushed. Finally, when DMA is present in the system, it must
be assumed that cycle stealing is occurring at every opportunity, thus inflating
instruction fetch times. Does this mean that these widely used architectural techniques
render a system effectively unanalyzable for performance? Essentially,
yes. However, by making some reasonable assumptions about the real impact of
these effects, some rational approximation of performance is possible.

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