7.2.7   Analysis of Sporadic and Aperiodic Interrupt Systems

Ideally, a system having one or more aperiodic or sporadic cycles should be
modeled as a rate-monotonic system, but with the nonperiodic tasks modeled as
having a period equal to their worst-case expected interarrival time. However,
if this approximation leads to unacceptably high utilizations, it may be possible
to use a heuristic analysis approach. Queuing theory can also be helpful in this
regard. Certain results from queuing theory are discussed later.

The calculation of response times for interrupt systems is dependent on a
variety of factors, including interrupt latency, scheduling/dispatching times, and
context switch times. Determination of context save/restore times is the same
as for any application code. The schedule time is negligible when the CPU
uses an interrupt controller with multiple interrupts. When a single interrupt
is supported in conjunction with an interrupt controller, it can be timed using
instruction counting.

7.2.7.1   Interrupt Latency    Interrupt latency is a component of response
time, and is the period between when a device requests an interrupt and when the
first instruction for the associated hardware interrupt service routine executes. In
the design of a real-time system, it is necessary to consider what the worst-case
interrupt latency might be. Typically, it will occur when all possible interrupts in
the system are requested simultaneously. The number of threads or processes also
contribute to the worst-case latency. Typically, real-time operating systems need
to disable interrupts while it is processing lists of blocked or waiting threads. If
the design of the system requires a large number of threads or processes, it is
necessary to perform some latency measurements to check that the scheduler is
not disabling interrupts for an unacceptably long time.

7.2.7.2   Instruction Completion Times     Another contributor to interrupt
latency is the time needed to complete execution of the macroinstruction that was
interrupted. Thus, it is necessary to find the execution time of every macroinstruction
by calculation, measurement, or manufacturer’s data sheets. The instruction
with the longest execution time in the code will maximize the contribution
to interrupt latency if it has just begun executing when the interrupt signal
is received.

For example, in a certain microprocessor, it is known that all fixed-point instructions
take 10 microseconds, floating-point instructions take 50 microseconds, and
other instructions, such as built-in sine and cosine functions, take 250 microseconds.
The program is known to generate only one such cosine instruction when compiled.
Then its contribution to interrupt latency can be as high as 250 microseconds.

The latency caused by instruction completion is often overlooked, possibly
resulting in mysterious problems. Deliberate disabling of the interrupts by the
software can create substantial interrupt latency, and this must be included in
the overall latency calculation. Interrupts are disabled for a number of reasons,
including protection of critical regions, buffering routines, and context switching.