Optical Switching

Chapter 3.2 - Design Alternatives For Optical Packet Switches

3.2   DESIGN ALTERNATIVES FOR OPTICAL PACKET SWITCHES

Numerous architectures for optical packet switches have been proposed in the literature.
This section presents the most important factors that differentiate switch architectures,
or stated otherwise, the design alternatives for optical packet switches.

3.2.1   Synchronous versus Asynchronous Optical Packet Switching

The most fundamental factor that distinguishes OPS networks is the overall
mode of operation. Optical packet switched networks can be divided into two
categories: slotted (synchronous) and unslotted (asynchronous). In a slotted network
all packets (also referred to as cells) have the same size. Each packet is placed,
along with its header, in a fixed-length timeslot, which has a longer duration than
the packet and header in order to include guard times. The switch fabric is reconfigured
at the beginning of each timeslot and all packets that arrived during the previous
timeslot are switched simultaneously [2]. This implies that all incoming
packets must be aligned in phase prior to switching.

Packets traveling on a fiber can experience different delays, depending on factors
such as fiber length, temperature variation, and chromatic dispersion. Chromatic
dispersion is the phenomenon in which different spectral components of a pulse
travel at different velocities. In other words, because of chromatic dispersion,
packets that are transmitted on different wavelengths experience different propagation
delays. The use of dispersion-compensating fiber alleviates the effects of
chromatic dispersion. The packet propagation speed is also affected by temperature
variations. Additionally, the delay incurred by packets within a switching node is
not fixed, as it depends for example on the amount of time a packet will have to
wait before its output can accommodate it. Owing to variant delays that packets
experience while traveling through the optical network, they arrive at switch
inputs unaligned. As a result, a slotted switch must employ synchronization units
at its inputs to align the incoming packets in phase with a local clock reference.
Synchronization is not an easy task in the optical domain.

The assumption of fixed-length traffic made in synchronous OPS networks is
problematic when the offered traffic is composed of variable-length information
units whose transmission time exceeds the slot time. One approach is to select a
slot size that fits the largest information unit. This, however, means that most
slots will be partially used when small-size information units are sent, thus
wasting network resources [3]. Another approach is to apply segmentation and
reassembly protocols at the optical network edges in order to create packets of a
specified length. This increases system complexity and can be a problem at very
high speeds. It must be noted that fixed-length packets are not well suited for
operation in an Internet environment with variable length IP datagrams.

The most important design parameter in a slotted packet switched network is
clearly the packet size. A large packet size results in a coarser switching granularity,
which could lead to bandwidth underutilization and increased latency (in the case
where packets are forced to wait at ingress routers until a packet of the specified
size is formed). If the packet size is chosen to be small, the control overhead
increases, as the packet switches are forced to process a large number of headers.
This leads to a decrease in the percentage of the bandwidth that is used to transport
packets. Another side effect of a small packet size is the increased probability
of contention in the control plane. Furthermore, the rate at which the switch
interfaces can read and update the packet header sets a limit to the maximum switching
speed. Normally, this is not an issue, as the reconfiguration time of the optical
fabric dominates the switching latency. It is clear that the choice of an optimum
packet size is a trade-off between a finer switching granularity and a reduced
control overhead [2].

FIGURE 3.1 Scheme for input synchronization at a node in a slotted network.


Synchronous networks generally achieve a fairly high throughput as the behavior
of the packets is regulated. However, complex and expensive synchronization
hardware is needed at each node [4]. Figure 3.1 shows a typical synchronization
stage consisting of a series of 2 × 2 switches and delay lines with decreasing
lengths to offer variable delays [5].

Packets in an asynchronous (unslotted) network do not necessarily have the same
size. Packets that arrive at the switch enter immediately (“on-the-fly”) without being
aligned; therefore, the switching operation can take place at any point in time,
instead of only at the start of a timeslot as in synchronous networks. The behavior
of packets in an unslotted network is not as predictable as in a slotted one, and as a
result there is a higher probability of contention, which in turn has a negative
impact on the network throughput and packet loss ratio. Asynchronous networks,
however, feature a number of advantages such as robustness and flexibility.
Furthermore, as a result of the asynchronous operation, the use of complex packet
synchronization units is avoided and so are the associated costs. On the negative
side, the switch control is more complicated in unslotted scenarios and the overall
performance is worse compared to a synchronous switching node of the same
size. This can be counteracted by carefully engineering the asynchronous switching
node and by designing an effective contention resolution scheme. Unslotted
networks generally require more complex scheduling algorithms, able to schedule
new arrivals on an asynchronous basis. In a sense, this represents a shift in complexity
away from the optical domain (as synchronization units are eliminated) and more
into the electronic/software domain [6].

Figure 3.2 illustrates simplified switch architectures for slotted (a) and unslotted (b)
networks. In these switches, a small portion of the incoming optical signal is tapped
and directed to the switch control unit, which performs the necessary control functions.
In Figure 3.2a, with the synchronous architecture, the two packets that enter
the switch are first aligned by passing through synchronization units and enter the
switch concurrently. No synchronization units are included in the unslotted architecture
(Fig. 3.2b). Incoming packets are delayed using fixed-length fibers while their
headers are being processed and the switch fabric is being reconfigured. The two
packets enter and exit the switch fabric at different times.

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