Chapter 3.8.3 - The Data-Vortex Packet Switch

3.8.3 The Data-Vortex Packet Switch

The data-vortex architecture [60–62] was designed specifically to facilitate optical
implementation by minimizing the number of switching and logic operations, and
by eliminating the use of internal buffering. The data-vortex is a multihop packet
switch that tightly couples the deflection method and a virtual buffering mechanism
to achieve hardware simplicity, scalability, and high throughput. This architecture
employs a hierarchical structure, synchronous packet clocking, and distributed-
control signaling to avoid packet contention and reduce the necessary number of
logic decisions required to route the data traffic. All packets within the switch
fabric are assumed to have the same size, and are aligned in timing when they
arrive at the input ports. The timing and control algorithm of the switch permits
only one packet to be processed at each node in a given clock frame and, therefore,
the need to process contention resolution is eliminated. The wavelength domain is
additionally used to enhance the throughput and to simplify the routing strategy.
Studies of the traffic flow within the switch architecture have shown that the data
vortex can efficiently scale to large port counts while maintaining a low packet
switching latency and a narrow latency distribution.

Because header bits run at the rather low packet rate, there is no requirement for
high-speed electronics within the node. Compared with TDM-encoded header bits,
the synchronization complexity can also be greatly relaxed within the packet-routing
process. A key design of the system is a distributed control signaling mechanism
among routing nodes to achieve bufferless operation and simple routing logic.
With the embedded synchronous timing, this scheme can schedule the traffic
flow of the neighboring nodes properly so that packet conflict is eliminated. To
implement the scheme, control lines are applied between any pair of nodes, which
have competitive output paths to the same node.

The data-vortex topology consists of routing nodes that lie on a collection of
concentric cylinders. The cylinders are characterized by a height parameter H
corresponding to the number of nodes lying along the cylinder height, and an
angle parameter A, typically selected as a small odd number (<10), corresponding
to the number of nodes along the circumference. The total number of nodes is H × A
for each of the concentric cylinders. The number of cylinders C scales with the
height parameter as C = log₂H + 1. Because the maximum available number of
input ports into the switch is given by H × A, which equals the available number
of output ports, the total number of routing nodes is given by H × A × (log₂H + 1)
for a switch fabric with input–output ports.

In Figure 3.13, an example of a switch fabric is shown. The routing tours are seen
from the top and the side. Each crosspoint shown is the routing node, labeled

FIGURE 3.13 The Data Vortex packet switch: (a) top view with A ¼ 5 and H ¼ 4; (b) side view with A ¼ 5 and H ¼ 4.

uniquely by the coordinate (a, c, h) where 0 ≤ a < A, 0 ≤ c < C, and 0 ≤ h < H.
Packets are injected at the outermost cylinder (c = 0) from the input ports, and
emerge at the innermost cylinder (c = log₂H = C - 1) toward the output ports.
Each packet is self-routed by proceeding along the angle dimension from the
outer cylinder toward the inner cylinder. Every cylindrical progress fixes a specific
bit within the binary header address. This hierarchical routing procedure allows
the implementation of a technique of WDM-header encoding, by which the
single-header-bit-based routing is accomplished by wavelength filtering at the
header retrieval process.

Each packet is self-routed in the fashion of binary-tree decoding as it propagates
from the outer cylinder toward the inner cylinder. The innermost cylinder allows
the packet to circulate around when the output buffers are busy. To avoid packet
contention, the switching architecture employs a synchronous and distributed
control mechanism to properly schedule the neighboring packet flow. As a result,
each node encounters at most one packet at a time and no optical buffering will
be necessary within the data vortex switch fabric. This also greatly simplifies the
routing procedure at each hop and facilitates the photonic implementation of the
architecture. Although packet deflection occurs because of the need for traffic
control, the probability of that event and its incurred latency penalty are minimized.
This is achieved because packets are provided with multiple paths to the destination
and the topology provides as low as two hops of latency penalty in the case of
deflection. Because packets are always allowed to stay on the same cylinder if
they are deflected, the “angle” dimension virtually provides a buffering mechanism
for the packets while eliminating the potential packet conflict.

Packets are processed synchronously in a highly parallel manner. Within each
timeslot, every packet within the switch progresses by one angle forward in the
given direction either along the solid line toward the same cylinder or along
the dashed line toward the inner cylinder. The solid routing pattern at the specific
cylinder shown can be constructed as follows. First, we divide the total number of
nodes along the height H into 2c subgroups, where c is the index of the cylinder.
The first subgroup is then mapped as follows. For each step, we map half of the
remaining nodes at angle (a) from the top to half of the remaining nodes at angle
(a + 1) from the bottom in a parallel way. This step is repeated until all nodes of
the first subgroup are mapped from angle (a) to angle (a + 1). If multiple subgroups
exist, the rest of them copy the mapping pattern of the first subgroup. The solid
routing paths are repeated from angle to angle, which provide permutations
between “1” and “0” for the specific header bit. At the same time, due to the
smart twisting feature of the pattern, the packet-deflection probability is minimized
because of the reduced correlation between different cylinders. The dashed-line
paths between neighboring cylinders maintain the same height index h because
they are only used to forward the packets. By allowing the packet to circulate, the
innermost cylinder also alleviates the overflow of the output-port buffers.

The avoidance of contention, and thereby reduction of processing necessary at
the nodes, is accomplished with separate control bits. Control messages pass
between nodes before the packet arrives at a given node to establish the right of
way. Specifically, a node X on cylinder c has two input ports: one from a node Y on
the same cylinder c and one from a node Z on the outer cylinder i -1. A packet
passing from Y to X causes a control signal to be sent from Y to Z that blocks
data at Z from progressing to X. The blocked packet is deflected and remains on
its current cylinder level. As mentioned above, the routing paths along the angle
dimension provide permutations between “1” and “0” for the specific header bit.
Therefore, after two node hops, the packet will be in a position to drop to an
inner cylinder and maintain its original target path. The control messages thus
permit only one packet to enter a node in any given time period. Because the
situation of two or more packets contending for the same output port never occurs
in the data vortex, it significantly simplifies the logic operations at the node and,
therefore, the switching time, contributing to the overall low latency of the
switching fabric. Similar to convergence routing, the control mechanism and the
routing topology of the data-vortex switch allow the packets to converge toward
the destination after each routing stage. The fixed priority given to the packets at
the inner cylinders by the control mechanism allows the routing fairness to be
realized in a statistical sense. The data vortex has no internal buffers; however,
the switch itself essentially acts as a delay-line buffer. Buffers are located at the
input and output ports to control the data flow into and out of the switch. If there
is congestion at an output buffer, the data waiting to leave to that buffer circulate
around the lower cylinder and, thus, are optimally positioned to exit immediately
as soon as the output ports are free.

< Previous Excerpt Next Excerpt >

Purchase This Book

TABLE OF CONTENTS

Chapter 3.8.3 - The Data-Vortex Packet Switch

Contact Preferences

This is embarrasing...

Customize Your GlobalSpec Experience

Select Your Free Newsletters

Industry Newsletters

Select Your Free Product Alerts

This is embarrasing...