Chapter 3.8 - Optical Packet Switch Architectures

3.8 OPTICAL PACKET SWITCH ARCHITECTURES

This section presents three indicative optical packet switch architectures that have
been studied extensively in the context of research projects, and implemented in
optical testbeds.

3.8.1 KEOPS

The ACTS (Advanced Communications Technologies and Services) KEOPS
(KEys to Optical Packet Switching) project succeeded the ATMOS (ATM Optical
Switching) project and extended the study of a packet-switched optical layer.
KEOPS addressed the analysis and demonstration of bit rate optical transparent
packet switching within all-optical network architectures, by means of network
and system studies and laboratory demonstrators based on components developed
in the project [56–58].

In KEOPS, the duration of the packets is fixed; the header and its attached payload
are encoded on a single wavelength carrier. The header is encoded at a low fixed bit
rate (e.g., 622 Mb/s) to allow the utilization of standard electronic processing. Routing
information is derived from the packet header after optoelectronic conversion. The
payload duration is fixed, regardless of its content; hence, the volume of data
carried in each packet is proportional to the user-defined bit rate, which may vary
from a few hundred megabytes per second to 10 Gb/s, with easy upgrade capability
[57]. The fixed packet duration ensures that the same switch node can switch packets
with variable bit rates. Consequently, the optical packet network layer proposed in
KEOPS can be considered both bit rate and, to some degree, also transfer mode transparent,
e.g., both ATM cells and IP packets can be switched [1].

KEOPS suggests a 14-byte packet header. Of that, 8 bytes are dedicated to a
two-level hierarchy of routing labels. Then, 3 bytes are reserved for functionalities
such as identification of payload type, flow control information, packet numbering
for sequence integrity preservation, and header error checking. A 1-byte pointer
field flags the position of the payload relative to the header. Finally, 2 bytes are
dedicated to the header synchronization pattern [1].

The optical packets used in the optical layer are placed into a fixed-duration timeslot,
allowing for a synchronous operation of the switching nodes. Guard times are
also inserted to account for the optoelectronic device switching time, the jitter
experienced by the payload in the nodes (mainly in the FDLs), and the finite
resolution of the synchronization units at the network/node interfaces [56].
Each node in the KEOPS network has the following subblocks:

an input interface that aligns the incoming packet streams relative to the switch
master clock, creating synchronous packet flows while properly recovering
the header content;
a switching core that routes the packets to their proper destination, resolves
contentions using FDLs, and manages the introduction of dummy packets to
keep the system running in the absence of useful payload; and
an output interface that reattaches the updated headers to the packets and
ensures that physical transmission constraints are met, including power
levels, wavelength allocation, and signal shaping.

In the KEOPS node architecture, a coarse and slow synchronization unit is placed
at each incoming link of a node (after wavelength demultiplexing has been
performed) in order to compensate for the static phase differences due to the link
length and the wavelength used and for the phase wander due to temperature
variations. Each of these units is followed by a fast and fine synchronization unit,
which compensates the packet-by-packet time variations (jitter) resulting from the
use of different wavelengths for the routing and buffering processes in the previous
nodes [56].

As the node itself may introduce jitter among packets, a fine synchronizer may
also be necessary, at each node output, in order to restore the correct packet
cadence, or at the network boundaries to recover the payload. The input synchronizer
is realized using switchable FDLs of different lengths (in decreasing exponential
sequence). The first section acts slowly and recovers only the fixed part of the
delay, the second part is set, packet by packet, and recovers the varying part of
the misalignment. The fine synchronizer is realized by means of a tunable wavelength
converter and a high-dispersion fiber. The electronic control assigns a
proper wavelength to the outgoing packet in order to compensate for the jitter of
the signal, with the delay accumulated inside the high-dispersion fiber [56].

Two different switch architectures (wavelength routing and broadcast-and-select)
have been proposed and demonstrated in the context of KEOPS. The wavelength
routing switch utilizes dynamic wavelength conversion at the packet level
to perform the routing of packets from each inlet to their destination outlet. A wavelength
converter, together with a demultiplexer, implements a 1 × W space switch,
with W being equal to the size of the wavelength comb. Packets from different inlets
may compete at a given timeslot for the same output. In the wavelength routing
switch, such contentions are resolved with the aid of an FDL buffer. The structure
and dimensioning of this buffer are of prime importance to the performance of
the switch, in terms of packet loss probability [56]. The switch operates on a
timeslot basis; therefore the input packets should be aligned within the local timeslot
with an accuracy of a few bytes. Alignment at the bit level is not required as the
header can be recovered on the fly, owing to the synchronization patterns at the
header beginning.

Packet routing is performed through two successive wavelength conversion
stages. At the first stage, incoming packets are routed to a delay line with an
appropriate delay (the shortest possible), and in the second stage they are routed
to their destination output. The routing and buffering algorithm minimizes the
delay in the switch, taking into account the following constraints: two packets
cannot be routed to the same output at a given timeslot and the order of packets
must not be disturbed [56].

The broadcast-and-select packet switch suggested in KEOPS is depicted in
Figure 3.11. This switch relies on the use of wavelength encoding and fast wavelength
selection in order to achieve packet routing and on the exploitation of
optical FDLs accessed through fast optical gates, to perform packet buffering.
The N × N switch consists of three sections: the wavelength encoder, the buffer
and broadcast section, and the wavelength selector block. The wavelength encoding
block consists of N wavelength converters, one per input. Each one encodes its
packets on a fixed wavelength. The cell buffer block comprises B FDLs followed

FIGURE 3.11 Architecture of the broadcast-and-select switch suggested in the project

by a space switch stage, realized using SOAs operating as fast gates. The SOAs
select packets from the correct delay lines and send them to the correct outputs
under electronic control. The last block, the wavelength selector block, consists of
N demultiplexers, which forward the different outputs to SOA gates before
the signals are recombined, thus selecting packets from the correct inputs [57].
The principle of operation is as follows. Each incoming packet is assigned one
wavelength, identifying its input port, and then fed into the FDL buffer. All
packets are broadcast to all delay lines and thus made available during B consecutive
timeslots. The buffer gates select one timeslot, corresponding to the appropriate
delay as determined from actual traffic conditions at the input. Finally, the wavelength
selector only discriminates as to one outgoing packet at a time, on the
basis of its wavelength, that is, its input address [56].

In the broadcast-and-select architecture, a copy of each packet is available at
each output; therefore multicasting can be supported with no additional effort.
However, because of the power loss due to splitting, the product of the number of
wavelengths and the number of ports cannot be high, thereby limiting the scalability
of the switch [15].

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