Optical Switching

chapter 3.4 General Architecture Of An Optical Packet Switch

3.4   GENERAL ARCHITECTURE OF AN OPTICAL PACKET SWITCH

Figure 3.5 shows a generic architecture of an optical packet switch. This switch
consists of three main blocks:

  • Cell encoder. Packets arriving at the switch inputs are selected by a demultiplexer,
    which is followed by a set of tunable optical wavelength converters
    that address free space in the output buffers. Optical-to-electrical interfaces
    situated after the demultiplexers extract the header of each packet where the
    packet’s destination is written and thus determine the proper switch outlet.
    This information is used to control the switch. If synchronous operation is
    desirable, optical packet synchronizers must be placed at the switch inputs.
  • Nonblocking space switch. This switch is used to access the desired outlet as
    well as an appropriate delay line in the output buffer. The size of the space


    FIGURE 3.5 A generic optical packet switch architecture.


    switch in terms of gates is NW × N(B + 1), where N is the number of input and
    output fibers, W is the number of wavelengths per fiber, and B is the number of
    fiber delay lines.
  • Buffers. The switch buffers are realized using fiber delay lines.

Packets that arrive in a packet-switching node are directed to the switch’s input
interface. The input interface aligns the packet so that they will be switched correctly
(assuming the network operates in a synchronous manner) and extracts the routing
information from the headers. This information is used to control the switching
matrix. The switching matrix performs the switching and buffering functions.
The control is electronic, because optical logic is in too primitive a state currently
to permit optical control. After the switching, packets are directed to the output
interface, where their headers are rewritten. The operating speed of the control
electronics places an upper limit on the switch throughput. For this reason, it is
imperative that the packet switch control scheme and the packet scheduling
algorithms are kept as simple as possible [1].

Figure 3.6 depicts a more detailed view of the general architecture of a WDM
packet switch as described earlier. This particular implementation is based on
splitters, SOA gates and couplers. The state of the SOA gates is manipulated to
direct packets to fiber delay lines of appropriate lengths and/or the desired
outputs. In the paragraphs that follow, the functionality of the switch blocks is
described more extensively.


FIGURE 3.6 A detailed view of the general architecture of a WDM optical packet switch.


The input interface of an optical packet switch should be able to perform the
following functions [14]:

  • 3R regeneration of the incoming signal in order to restore signal quality before
    subsequent processing and switching;
  • wander/jitter extraction;
  • packet delineation in order to identify the beginning and end of each packet
    as well as the beginning and end of its header and payload;
  • synchronization of packets and alignment within the switching time slots
    (if the network operates in a synchronous manner);
  • separation of the header, which is directed to the control unit for processing;
    and
  • conversion of the external wavelength (transmission wavelength) of the
    packet to an internal wavelength pertinent to internal use in the switch
    fabric, if necessary (i.e., if the switch fabric is wavelength selective).

The control unit processes the header information and issues all necessary commands
to configure the switch fabric accordingly. In order to do so, it consults
forwarding tables that are maintained at each node and which are updated by the
network management system. The control unit also performs header update and
forwards the new header to the output interface. The new header identifies,
among other things, the next node in the packet path. These control functions are
at present implemented by electronics. The switch fabric transparently switches
the payload in accordance with the commands of the control unit. Finally, the
output interface may perform the following functions [14]:

  • 3R regeneration, to regain signal quality after deterioration due to component
    imperfections and crosstalk in the switch fabric;
  • attachment of the new header to the associated payload;
  • packet delineation and resynchronization;
  • conversion of internal wavelength to an external one, if necessary; and
  • output power equalization (as signal power levels will vary because of different
    paths and insertion losses through the switch fabric).

 

UNLIMITED FREE
ACCESS
TO THE WORLD'S BEST IDEAS

SUBMIT
Already a GlobalSpec user? Log in.

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.

Customize Your GlobalSpec Experience

Category: Fiber Optic Cables
Finish!
Privacy Policy

This is embarrasing...

An error occurred while processing the form. Please try again in a few minutes.