TABLE OF CONTENTS Functional verification plays a key role in meeting an aggressive chip design schedule and achieving cost and quality goals. Because functional verification is a critical part of all complex chip designs, to achieve these lofty targets the functional verification team must have a deep understanding of the chip design and a robust process. This process is the Verification Cycle. The process is cyclic, providing feedback from past projects, allowing the verification team to continually improve their process and environment.
Part One begins by describing the verification challenges and introducing the Verification Cycle. Chapters 2 and 3 describe basic verification strategies central to all techniques and the simulation-based components commonly used throughout the Verification Cycle. Chapter 4 details the verification plan the first part of a project cycle containing the strategy, methods, and requirements for the project.
Functional verification has become a major challenge in the chip and system design arena. As engineers place more and more function in increasingly dense chips, the discipline required for successful chip and system verification has advanced. As a result, the verification engineer, little known 10 years ago, has become a treasured member of the chip design team.
This chapter introduces verification tasks, illustrated with basic examples; their challenges; and the defined process behind functional verification. These challenges require a controlled verification process, with continuous feedback for improvements. This...
