TABLE OF CONTENTS With a solid understanding of functional verification techniques for creating robust environments, the next steps in the Verification Cycle are the regression stage, the tape-out readiness checkpoint, debugging the fabricated hardware, and escape analysis. These stages provide a backdrop for the verification team to reflect upon the strengths and weaknesses of their environments, both before tape-out and after receiving hardware results. Chapter 13 focuses on these parts of the Verification Cycle.
The most complex designs require advanced functional verification techniques. These techniques include high-level model verification before register transfer level implementation, bootstrapping simulation efforts, and coverage directed stimulus generation. These are the topics of Chapter 14.
The verification team spends most of their effort in the first half of the verification cycle. Weeks of planning lead to a sound verification plan that, in turn, yields a robust verification environment. Building that environment and debugging the DUV take the lion's share of the verification effort. As the team completes the environment, they focus their efforts on sweeping the design of the last bugs before initial hardware fabrication. However, the verification cycle continues well beyond fabrication, as the design team tests the fabricated hardware and prepares for final manufacturing.
Before hardware tape-out, the verification team completes sections of their test plans as they verify the entire chip or system's functional specification. In most complex systems that require hierarchical verification, lower level test plans complete before system...
