TABLE OF CONTENTS Within the Verification Cycle, the verification team spends most of their time developing the verification environment and debugging the HDL. Having completed the verification plan, the team embarks on creating robust stimulus and checkers in their quest for delivering a bug-free hardware design. Because of the depth of effort needed to develop a verification environment and debug both the HDL and verification environment, Part 2 and Part 3 of this book focus squarely on these two portion of the Verification Cycle.
Simulation based verification is the most widely used method of functional verification. At the heart of this methodology is the simulation engine, which allows the verification team to model the behavior of the design. Other critical tools support the simulation method, including High-level Verification Languages, debugging software and coverage modelers. Within Part 2, Chapter 5 and 6 describe these simulation-based verification tools.
Robust simulation tools provide a platform upon which skilled verification engineers create stimulus and checking components that verify the correct design behavior. Verification engineers have multiple techniques available for creating these components. Chatpers 7 and 8 explain these varying methods, citing multiple examples, including a second Calc design. Chapter 8 also delves into the debug process used when the environment detects a difference...
