TABLE OF CONTENTS A customer expects the verification "warranty" to last the life of the system. At the same time, the limited number of simulation cycles (compared to the life of the system) handicaps the verification effort. To combat this, the verification team needs a robust strategy for creating stressful stimulus during the relatively small number of available simulation cycles. However, the additional challenge beyond creating the stimulus is that the environment must identify all the bugs triggered by this stress. Driving the stimulus is only half of the equation. Remember the yin and yang of verification: not only must the stimulus aggravate the DUV, the checking components also must recognize when a bug exists in the design.
After creating the stimulus and checking components, the verification team can begin to debug the hardware description language (HDL) and the verification components. When the results of the design under verification (DUV) and the checking component disagree, the verification engineer must investigate the miscompare. This investigation is the debug phase, and during this phase, the verification team reaps the fruits of their component-building labor.
This chapter describes methods for checking complex designs using simulation. The Calc2 design is used to demonstrate multiple verification techniques that were introduced in Chapter 3 for results checking. The chapter then introduces the debug process and how choices in the verification strategy effect debug.
During the planning phase of the verification test bench, verification leaders must make the basic choices on stimulus generation. These...
