TABLE OF CONTENTS Before exploring the details of the verification cycle's simulation-based strategies, this chapter and Chapter 6 discuss the typical design automation (DA) tools that are available to the design and verification teams. First, we introduce the major characteristics of hardware description languages (HDLs) and their simulation engines, which provide the heart of the simulation-based verification cycle. Newer DA technologies that allow the formal verification of a DUV are the focus of Chapters 11 and 12.
Design engineers normally use an HDL to define the function and the structure of a design under verification (DUV). Specifying a design in the text format of an HDL, an activity called design entry, allows the engineer to document the DUV unambiguously and later execute it as a model in a simulation engine. The HDL version of the DUV is also the basis for the physical implementation of the design. To better support the simulation task, HDLs have features that go beyond the mere description of the design and include the specification of stimulus and checking components, which form an HDL test bench. When we characterize the typical elements of HDLs as design specification tools in this chapter, we compare and contrast the two most popular HDLs, VHDL and Verilog, as prime examples.
Figure 5.1 is used to guide the discussion from design entry through the simulation-based verification cycle. The simulation engine is at the heart of simulation-based verification. It executes the HDL model in conjunction with the HDL test bench elements a user...
