OVERVIEW

This second part of the overview of tools for simulation-based verification focuses on the simulation environment. A walk through the landscape of test bench writing serves two purposes. First, there is a general overview of the requirements for tools in this area. The main goal is to understand the principles of how languages and libraries can support well-structured test benches and higher productivity of verification teams. Second, interleaved with this discussion is a walkthrough of several available test bench writing tools and languages. We cover test bench aspects of hardware description languages, the e language, OpenVera, and SystemC.

Because there are a multitude of tools available, there is no room to cover every single one in detail. Instead, as the different areas of test bench writing are discussed, the chapter switches between different tools and highlights some of their specific properties. However, the goal of this section, and thus the thread of the discussion, is to gain an understanding of the challenges and the common features of these tools. Although the chapter looks at some of the distinguishing features of the tools discussed, the focus is on this class of tools as a group and not on detailed specifics of a single one of them. This is still an emerging, ever-changing field of technology, and it is more important to have a framework of the key concepts than a reference manual on specifics, which will be outdated quickly.

The ultimate measure for quality of a verification effort...