4.7 VIRTUAL-TO-PHYSICAL ADDRESS TRANSLATION

An important detail avoided so far is the translation of a virtual address in the process to a physical address in memory. As previously explained, only a few pages, not the entire process, reside in memory at any one time. This section describes the algorithm used to locate the pages in memory in two ways: first, by partially tracing execution of a simple instruction, and second, by looking at the functions of the supporting hardware.

Tracing an instruction's execution requires assembly language experience. Examine a single instruction, INCL A, located in the middle of a virtual page in Figure 4.15. This instruction increments the variable "A," a 32-bit quantity. For this discussion, the instruction is on page 1 and the variable is on page 3. In the figure, the instruction begins 119 bytes into page 1 and the variable is located 408 bytes into page 3. In the center of the illustration, the image is contiguous in virtual address space; page boundaries are invisible and unimportant. The physical view of memory is shown on the right of the figure; two of the image's pages are scattered in memory because the image is neither contiguous nor totally resident. Scattering pages in memory is a major advantage of paging systems. To support this feature, some mechanism must translate or map the virtual addresses into physical addresses. In other words, the system must keep a record of where the pages have been placed in physical memory so...