4.10 VAX ADDRESS TRANSLATION

To this point, the paging logic has been simplified so that several other vital points might be presented. This section examines the VAX hardware address translation algorithm in detail. To support translation, six registers of the internal processor register (IPR) set are used to locate page tables-a pair for each of the regions, PO, P1, and SYS. One register of the pair contains the address of the appropriate page table; the other register contains its length. The PO and P1 pairs are part of the process' context; hence, they are saved in and restored from the hardware PCB at every context switch. This is how the process maintains its own private page tables. The SYS page

Figure 4.26: Page tables are used to reference the entire process

table is shared because OpenVMS is shared and implicitly part of every process.

Two figures are used in this description; all numbers on them are hexadecimal. Refer to Figure 4.27 first. The Program Counter (PC) contains the Virtual Address (VA), which needs to be converted to a Physical Address (PA). The upper two bits of the Virtual Address determine which of the three page tables are to be used. In this example, the PC value of 42,90A refers to the P0 region because the two high-order bits are zero. Circle 1 suggests that the page number (214) is extracted from the PC and checked against the P0 length register (POLR) to ensure that the PC address is in the...