2.1 INTRODUCTION

Metal thin films are integral parts of all microelectronics devices. They have been used in microelectronics devices such as ohmic contact, Schottky barrier contact, gate electrode, interconnect, diffusion barrier, adhesion layer and anti-reflecting layer.

With the advance in semiconductor device fabrication technology, the shrinkage in linewidth continues at a fast pace. According to the prediction of the roadmap by the Semiconductor Industry Association (SIA) in 2003, in the 0.13 ?m generation devices, the gate length and thickness of silicide at the contact window are 50 and 25 nm, respectively. In the year 2007 for the 90 nm generation devices, these numbers will further decrease to 40 and 20 nm, correspondingly (TABLE 2.1) [1]. Further, more transistors will be incorporated in one chip. In addition, owing to the demand for increased integration level, the surface area was not adequate to meet the interconnect demand. Multilevel interconnections provide flexibility in circuit design and a substantial reduction in die size and thus chip cost. FIGURE 2.1 shows a scanning electron microscope (SEM) cross-section of a six-level metal backend structure. Electrical connection between the various metal layers is provided by vertical interconnects commonly referred to as vias.