8.1 OVERVIEW

The swift and continuous progress of silicon-on-insulator (SOI) technology in recent years has made it competitive to bulk silicon technology for ULSI applications. Some of the inherent properties in favour of SOI technology over bulk include the reduction of junction capacitance, the ease to make shallow junctions, radiation hardness, and latch-up immunity [1]. The ultra-thin silicon film also results in reduction of the short-channel effects, which cause the gate to lose channel control with decreasing gate length and prevent scaling into the deep sub-micron regime. These advantages boosted SOI from merely a substitute for silicon-on-sapphire (SOS) to achieving acceptance in military applications and beyond.

However promising SOI technology may have become, there are always challenges that deter the widespread acceptance of SOI semiconductors. When scaling guidelines of SOI suggest that thinner films enjoy more improved sub-threshold slopes and reduced drain-induced-barrier-lowering (DIBL) than thicker fully depleted films [2], one major obstacle is the ability to obtain low source/drain series resistance. A high series resistance can easily offset the advantages to be gained from using the ultra-thin SOI material and it seriously degrades SOI current drivability. This is especially severe for short channel devices.

To overcome this problem, silicide technology on SOI devices has been developed and investigated. In this chapter, the SOI silicide technology is described. Starting from the review of silicide design analysis on SOI CMOS, challenges to implement existing bulk silicide technology to SOI devices are introduced. Then various silicide technologies on...