SilicideTechnology for Integrated Circuits
This detailed text provides guidance on the development and application of metal silicide technology as it emerges from the scientific to the prototype and manufacturing stages.
TABLE OF CONTENTS SilicideTechnology for Integrated Circuits
5.8: DEVICE CHARACTERISATION
5.8 DEVICE CHARACTERISATION
In this section, we highlight the advantages and challenges of a NiSi process using both electrical and physical characterisation of devices in narrow dimensions. As mentioned above, the inherent advantages of NiSi over its predecessors, TiSi 2 and CoSi 2, include the lower resistivity, lower Si consumption, lower thermal budget, lower contact resistance and lack of increase in sheet resistance with narrower poly-Si linewidths. One should not infer from this that NiSi is easily inserted in place of CoSi 2 since multiple challenges are associated with its use in device fabrication, ranging from the undesired agglomeration of NiSi films and the formation of NiSi 2 at low temperatures, to some excessive Ni diffusion either on narrow Si(100) areas or poly-Si lines leading to junction leakages that may become abnormally high [59, 82].
5.8.1 Addressing the device roadmap
In the device development community, the use of NiSi is viewed in terms of the technology node at which it can be inserted and in terms of a product upon which it can be qualified. As the device community continues to scale down the devices, the requirements for silicide contacts become more stringent. The integration challenges for the silicide are best described by the International Technology Roadmap for Semiconductors (ITRS) [179] and are presented in TABLE 5.3. This table highlights important device requirements (first column) related to the device contacts for the 130, 90 and 65 nm technology nodes (defined here as the half-pitch of the...
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