TABLE OF CONTENTS CICERO S. VAUCHER
Philips Research Labs, Prof. Holstlaan 4,
5656AA Eindhoven, Netherlands
cicero.vaucher@philips.comJAN-PETER FRAMBACH
Philips Semiconductors,
Nijmegen, Netherlands
jan-peter.frambach@philips.comJOHAN D. van der TANG
Eindhoven University of technology,
Eindhoven, Netherlands
j.d.v.d.tang@tue.nl
This paper focuses on high performance architectures and building blocks for clock and data recovery (CDR) applications. After a review of basic concepts, a parallel CDR architecture for high operation speeds and low-power dissipation is introduced, followed by discussion of linear detectors for multiple octave operation CDR systems. A frequency acquisition architecture, based on standard PLL building blocks, is then presented. Finally, multi-phase and wide-tuning-range oscillators are discussed.
Keywords: Clock-data recovery; phase-locked loop; phase detector; frequency detector; voltage controlled oscillator; multi-phase oscillator.
The purpose of a clock and data recovery (CDR) circuit is to extract a clock from an incoming data stream and sample the received data with the extracted clock, so as to be further processed in a synchronous manner. A CDR thus performs two tasks, clock recovery from a raw data stream and (bit) synchronization of the raw data stream. The retimed data stream is now suitable for further signal processing, such as byte alignment, frame synchronization, overhead processing, payload extraction and overhead based system performance monitoring.1 Although several ways exist to perform clock recovery, for example based on non-linear processing and SAW niters, monolithic implementations are usually based on a Phase Locked Loop (PLL).2 , 3
In this paper, we will concentrate on a parallel CDR architecture which leads to higher operation...
