TABLE OF CONTENTS ILS protocol technology has been described up to the previous section. And the LAN-PHY LSI and the optical transceiver module embedded with ILS have been developed to make it easy to implement ILS in optical transport systems or Ethernet equipment. This section described the 10GbE LAN-PHY LSI with ILS, focusing on its device and circuit technologies to achieve very high speed and low power as well as ILS implementation.
We have developed 10GbE-LAN PHY chip featuring ILS function. We adopted HTI(Hybrid-Trench Isolation)-SOI(Silicon On Insulator) process technology for the PHY chip. Fig 14. shows the cross-sectional view of HTI-SOI device 23.
The HTI consists of partial trench and full trench isolations. The body potential of the MOS transistors is fixed through the silicon layer under the partial trench isolation oxide. The HTI-SOI structure can thus suppress the floating body effect such as history effects, and the design layout of cell-library of bulk-device is easily translated to HTI-SOI device. Full trench isolation is applied for the boundary between nMOS and pMOS, analog circuit and digital circuit, and so on, in order to drastically suppress the latch-up and cross-talk noise. It is important for PHY chip to have endurance against latch-up because most telecommunication system is required to be hot-pluggable.
Besides, since HTI-SOI has a SOI structure, the device has a high-speed performance. Fig. 15 shows the fmax performance compared with bulk device. The fmax of HTI-SOI is...
