TABLE OF CONTENTS The traditional synthesizer consists of a single loop and the step size of the output frequency is equal to the reference frequency at the phase detector. Figure 7.1 shows this classic approach.
Wireless applications with a step size of 200 kHz have made the life of the designer somewhat easier, since such a wide step size reduces the division ratio. As can be seen in Figure 7.1, the simplest form of a digital synthesizer consists of a voltage-controlled oscillator (VCO). For PLL applications, the oscillator sensitivity, typically expressed in megahertz per volt (MHz/V), needs to be stated. For high-performance test equipment applications, the VCO is frequently provided in the form of a YIG oscillator. These oscillators operate at extremely high Q and are fairly expensive. The VCO needs to be separated from any load by a post amplifier, which drives a sine-wave-to-logic-waveform translator.
Typically, an ECL line receiver or its equivalent would serve for this function. This stage, in turn, drives a programmable divider and divides the oscillator frequency down to a reference frequency, such as 200 kHz. Assuming an oscillator frequency of 1 GHz, the division ratio would be 1 GHz/200 kHz = 5000. We will address this issue later. In Figure 7.1, however, we are looking at a 3 GHz output frequency and a step size determined by the reference source resolution, assuming a fixed division ratio.
The phase detector, actually phase/frequency detector (PFD), is driven by the reference frequency on...
