7.3 Noise and Performance Analysis of PLL Systems

To illustrate the effectiveness of CAD tools in PLL analysis, let us consider the design of a PLL synthesizer operating from 110 to 210 MHz. A reference frequency of 10 kHz is used, and the tuning diode has a capacitance range from 6 to 60 pF. For performance reasons we select a type 2 third-order loop. The phase calculations use Leeson's model [7.10] for oscillator noise and the following equation

(7.51)

Where:<i class="emphasis">L</i>(<i class="emphasis">f</i><sub<i class="emphasis">m</i></sub>)<i class="emphasis"> </i>= ratio of sideband power in 1-Hz bandwidth at<i class="emphasis"> f</i><sub<i class="emphasis">m</i></sub> to total power in dB<i class="emphasis">f</i><sub<i class="emphasis">m</i></sub> = frequency offset<i class="emphasis">f</i><sub0</sub> = center frequency<i class="emphasis">f</i><sub<i class="emphasis">c</i></sub> = flicker frequency of the semiconductor<i class="emphasis">q</i><sub<i class="emphasis">load</i></sub><i class="emphasis"> </i>= loaded <i class="emphasis">Q</i> of the tuned circuit<i class="emphasis">F </i>= noise factor<i class="emphasis">kT </i>= 4.1   10<sup-21</sup> at 300 K (room temperature)<i class="emphasis">P</i><sub<i class="emphasis">s av</i></sub> = average power at oscillator output<i class="emphasis">R </i>= equivalent noise resistance of tuning diode<i class="emphasis">K </i>= oscillator voltage gain

The lock-up time of a PLL can be defined in many ways. In the digital loop, we prefer to define it by separating the frequency lock, or pull-in, and the phase lock and adding the two separate numbers. To determine the pull-in time, a statistical approach can be used, defining a new gain constant K ² = V _B /2 ?f, where V _B is the supply voltage and f the frequency offset. The phase-lock time is...