TABLE OF CONTENTS The rapid advancements in microprocessor and digital signal processing technologies have permitted large-scale integration of oscillator systems for receivers of all types. Reduction of a complex PLL system to a single device (plus a small number of supporting external components) offers a number of design benefits, not the least of which are reduced system complexity and lower overall cost.
An example of the trend in receiver design toward highly integrated systems through the use of dedicated chipsets can be found in the IS-54 time division multiple access (TDMA) chipset for cellular radios (Philips). TDMA uses the same 30-kHz channel spacing as the old North American analog frequency division multiple access (FDMA) system, but multiplexes users over time. At different time intervals, multiple users may be present on the same frequency. The main benefit of this technology is an increase from one to three users per channel.
The overall block diagram of a second generation PCS dual-band triple mode radio chipset is given in Figure 7.87. The chipset combines all of the necessary RF and IF functions into four integrated devices. For the purposes of this chapter, we will focus on the dual frequency synthesizer chip (SA7025).
A detailed block diagram of the low-power synthesizer is shown in Figure 7.88. The IC is fabricated using the QUBiC (Philips) BiCMOS technology. The SA7025 features fractional- N with selectable modulo five or...
