7.4 Multiloop Synthesizers

To avoid the limitations of the single-loop synthesizer, synthesizers are often designed to employ more than one loop. Figure 7.83 shows a block diagram of a multiloop synthesizer. The first LO, operating from 81.4 to 111.4 MHz, is a two-loop synthesizer using a fre-

Figure 7.83: Block diagram of a multiloop synthesizer. ( Courtesy of Rohde and Schwarz.)

quency translation stage. It comprises a 70- to 80-MHz loop, a divider, two frequency translators, and an output loop at the final LO frequency. Two single-loop synthesizers are also used later in the receiver, but our discussion will be confined to the multiloop unit.

A 10-MHz crystal oscillator is used as the standard to which all of the internal oscillator frequencies are locked. A divide-by-100 circuit reduces this to a 100-kHz reference used in both loops of the synthesizer. The 100-kHz reference is further divided by 100 to provide the

1-kHz reference for the 70- to 80-MHz loop. The output of this loop is then further divided by 100 to provide 10-Hz steps between 0.7 and 0.8 MHz. This division improves the noise sidebands and spurious signal suppression of the loop by 40 dB.

The 0.7-to 0.8-MHz band is converted to 10.7 to 10.8 MHz by mixing it with the 10-MHz reference. A crystal filter is used to...