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[7.2] Thomas A. D. Riley, "Frequency Synthesizers Having Dividing Ratio Controlled Sigma-Delta Modulator," United States Patent, Patent No. 4,965,531, October 23, 1990.

[7.3] Nigel J. R. King, "Phase Locked Loop Variable Frequency Generator," United States Patent, Patent No. 4, 204, 174, May 20, 1980.

[7.4] John Norman Wells, "Frequency Synthesizers," European Patent, Patent No. 012579OB2, July 5, 1995.

[7.5] Thomas Jackson, "Improvement In Or Relating To Synthesizers," European Patent, Patent No. 0214217B1, June 6, 1996.

[7.6] Thomas Jackson, "Improvement In Or Relating To Synthesizers," European Patent, Patent No. W086/05046, August 28, 1996.

[7.7] Byeong-Ha Park, "A Low Voltage, Low Power CMOS 900 MHz Frequency Synthesizer," a Ph.D. dissertation, Georgia Institute of Technology, December 1997.

[7.8] Cris E. Hill, "All Digital Fractional-N Synthesizer for High Resolution Phase Locked Loops," Applied Microwave & Wireless, November/December 1997 and January/February 1998.

[7.9] Bar-Giora Goldberg, "Analog and Digital Fractional-n PLL Frequency Synthesis: A Survey and Update," Applied Microwave & Wireless, pp. 32-42, June 1999.

[7.10] D. B. Leeson, "A Simple Model of Feedback Oscillator Noise Spectrum," Proc. IEEE, vol. 54, pg. 329, February 1966.

[7.11] U. L. Rohde, Digital PLL Frequency Synthesizers,