TABLE OF CONTENTS The addition of two operands is the most frequent operation in almost any arithmetic unit. A two-operand adder is used not only when performing additions and subtractions, but also often employed when executing more complex operations like multiplication and division. Consequently, a fast two-operand adder is essential.
The most straightforward implementation of a parallel adder for two operands x n ?1, x n ?2 , x 0 and y n ?1, y n ?2 , y 0 is through the use of n basic units called full adders. A full adder (FA) is a logical circuit that accepts two operand bits, say x i and y i , and an incoming carry bit, denoted by c i , and then produces the corresponding sum bit, denoted by s i , and an outgoing carry bit, denoted by c i +1. As this notation suggests, the outgoing carry c i +1 is also the incoming carry for the subsequent FA, which has x i +1 and y i +1 as input bits. The FA is a combinational digital circuit implementing the binary addition of three bits through the following Boolean equations:
where ? is the exclusive-or operation, and
where x i y i is the AND operation, x i ? y i , and x i+ y i is the OR operation, x i ? y i
