TABLE OF CONTENTS Multiplication involves two basic operations: the generation of partial products and their accumulation. Consequently, there are two ways to speed up multiplication: reduce the number of partial products or accelerate their accumulation. Clearly, a smaller number of partial products also reduces the complexity, and, as a result, reduces the time needed to accumulate the partial products.
High-speed multipliers can be classified into three general types. The first generates all partial products in parallel, and then uses a fast multi-operand adder for their accumulation. This is known as a parallel multiplier. The second, known as a high-speed sequential multiplier, generates the partial products sequentially and adds each newly generated product to the previously accumulated partial product. The third is made up of an array of identical cells that generate new partial products and accumulate them simultaneously. Thus, there are no separate circuits for partial product generation and for their accumulation. This is known as an array multiplier, and it tends to have a reduced execution time, at the expense of increased hardware complexity.
To reduce the number of partial products (and hence reduce the amount of hardware involved and the execution time) we may examine two or more bits of the multiplier at a time. However, this scheme requires the generation of the multiples A, 2 A, and 3 A, where A is the multiplicand, as in Chapter 3. This reduces the number of partial products to n
