IXP1200 Programming: The Microengine Coding Guide for the Intel IXP1200 Network Processor Family

Some of the inter-microengine programming mechanisms examined in this chapter can be applied to communication and synchronization between microengines and the core. Specifically, the core on the IXP12xx can:
Perform atomic bit-test-and-set and bit-test-and-clear operations on SRAM, but not scratchpad memory.
Lock and unlock SRAM memory using the SRAM CAM lock mechanism.
Send inter-thread signals to microengine threads.
Push and pop the SRAM LIFOs atomically.
Even though the focus of this book is not programming the core, communication between the core and microengines can impact microengine programming. This section briefly covers how to program the core to interact with the inter-microengine programming concepts explored in this chapter.
Chapter 11 covers the microACE programming model. MicroACEs provide a framework for building packet-processing blocks. MicroACEs have both microengine and core components, and the framework provides a communication mechanism between them. Thus, we recommend looking into the microACE framework if you intend on performing microengine and core communication.
| Note | All of the successful microengine programs we have written interact with the core so that none of these synchronization mechanisms are required. Our priority has been to design our microengine and core data structures so that no synchronization was required between the core and microengines. This ensures that the fast-path microengine code never has to wait on the slow-path core code. Chapter 8 illustrates how data structures can be designed to accomplish this goal. |
Presenting core-programming examples represents a new challenge. What operating system, language and compiler...