IXP1200 Programming: The Microengine Coding Guide for the Intel IXP1200 Network Processor Family
This guide shows software engineers how to program the microengines of Intel s IXP1200 family of network processors.
TABLE OF CONTENTS IXP1200 Programming: The Microengine Coding Guide for the Intel IXP1200 Network Processor Family
Chapter 8: Fast Data Structure Processing
The goal of this chapter is to look at how some architectural features of the IXP12xx enable efficient processing of certain data structures. These data structures just happen to be commonly used in networking applications. The two data structures covered are just two examples of structures that perform well on an IXP12xx. Specifically, we ll look at hash lookup tables and circular queues.
Don t worry if you haven t had a data structures course recently, you won t be asked to prove the efficiency of a binary search. The data structures and techniques used in this chapter produce an Ethernet bridging microblock to replace the packet counting microblock we have been showing. Then we will combine this microblock with the receive microblock from the previous chapter and see how the performance has changed.
Architectural Considerations
A few architectural features of the IXP12xx enable efficient processing of certain data structures. Latency hiding is a powerful method for keeping the microengines busy while memory and I/O operations complete, maximizing parallelism allows the microengine threads to spend less time waiting for each other, and using the hardware hash unit allows microengine code to perform fast hashes.
Latency Hiding
An important feature of the IXP12xx microengines is the ability to hide the latencies associated with memory accesses and access to other hardware units. Hiding memory and other hardware access latencies allows a microengine thread to perform calculations in parallel with memory accesses. In some situations, latency hiding can completely mitigate the delays incurred while accessing memory.
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