IXP1200 Programming: The Microengine Coding Guide for the Intel IXP1200 Network Processor Family
This guide shows software engineers how to program the microengines of Intel s IXP1200 family of network processors.
TABLE OF CONTENTS IXP1200 Programming: The Microengine Coding Guide for the Intel IXP1200 Network Processor Family
Chapter 13: Next Generation IXP2xxx Hardware and Software
The goal of this chapter is to give you a sneak preview of the next generation of IXP series network processors. The first two processors from this family are the IXP2400 and the IXP2800, which we will refer to as the IXP2xxx. The IXP2xxx has many great new features, and we describe most of them here. Also, a lot of progress has been made in developing a good programming model for the microengines of these processors. Don t worry, the microblock model presented in the earlier chapters of this book still applies, but the new hardware enables some improvements. This model is described later in this chapter as well.
IXP2xxx Architecture
The block diagram for the IXP2800 is shown in Figure 13.1.
Figure 13.1: Block Diagram of the IXP2800
As you can see, the IXP2800 contains a familiar cast of characters. The microengines are still there, but they have been improved and there are more of them. The core is still there, although it is now an Intel XScale core instead of an Intel StrongARM core. The FBI remains but is renamed to the Media Switch Fabric (MSF) interface. The memory controllers are still there, but there are more of them and they have improved.
The next section is dedicated to the new microengines, called Microengine Version 2, or MEv2. The other hardware changes are briefly described as well. The detail given won t be enough to actually write code for these processors, but there is enough information to hopefully get excited...
Copyright Intel Corporation 2002 under license agreement with Books24x7
