Memory is used for inter-microengine information sharing. The application determines which memory type to use for inter-microengine information sharing.

Atomic memory operations, SRAM CAM locks, inter-thread signals, or any combination, can be used for inter-microengine synchronization. Atomic bit-test-and-set and bit-test-and-clear operations are available in scratchpad and SRAM memory.

SRAM CAM locks only work on SRAM and should only be used for temporary locks due to the implementation of a single lock fail queue in the SRAM unit.

Inter-thread signals can be sent between any two threads. A thread can wait for an inter-thread signal before continuing execution. A single inter-thread signal for a thread is queued and does not carry any information like the sending thread of the signal.

The core processor can make use of inter-thread signals and the SRAM atomic memory operations and CAM locks for core to microengine synchronization. The core can send an inter-thread signal to any microengine thread by writing the appropriate thread number into a CSR in the FBI. Reading and writing special memory regions from the core accesses the SRAM atomic memory operations and CAM locks. However, in general, data structures are designed to avoid any core-to-microengine synchronization.

By moving to inter-microengine programming, we are trading shared registers, with no access latencies, for shared memory, with noticeable access latencies. It seems inevitable that there is a performance penalty for this, unless we could somehow hide the memory latencies by having the microengine perform work during the times it accesses memory. This happens...