1.1 Introduction

Mixed-signal/radio frequency (RF) designs with complex digital and analog functionality, called systems-on-a-chip, (SoCs) are now in production in wireless applications. Future, integrated circuit (IC) technology scaling into deep submicron transistor dimensions benefit mixed-signal and RF radio frequency ICs with increased digital clock speed, increased maximum frequency of performance, and the ability to tune analog/RF sections with on-chip digital circuits. Growth in the mixed-signal/RF and the digital IC market is driven by a doubling of complexity (roughly halving in cost per logic function) every 24 to 36 months since 1965. The International Technology Roadmap for Semiconductors (ITRS) shows for an aggressive 2007 ASIC design, a 35-nm application specific IC, (ASIC) cell pitch, 3000 I/0 pads, ~7.0 GHz clock, 9 levels of metal, and a power supply of 0.7V [1]. However, RF microwave circuits are increasing in complexity at a much slower rate with little increase in device density. Power, noise, dynamic range, and device matching have contributed to keeping RF and microwave devices from shrinking in physical size. Migration from discrete device implementations using single-ended RF and microwave processing to integrated differential processing, is one factor enabling the proliferation of low-cost integrated wireless solutions through 5 GHz and creating the need for differential analysis tools.

As a result, wireless RF communication circuits and integrated circuits are becoming more complex and packing more functionality and signals into an ever-closer space. With ICs becoming larger, incorporating mixed-analog/RF functions and dense digital logic, there is a high-level of electromagnetic interaction between circuit...