TABLE OF CONTENTS The principal requirements of any high speed digital integrated circuit technology allowing the realization of large scale integration are:
A low chip area per logic gate;
A low gate power dissipation;
A low speed-power product;
A low gate propagation delay; and
A high yield.
The ultra-high-speed, low power performance requirements for the next generation of electronic systems and computers depend on the exploitation of the tremendous strides that have been made recently in MESFET and HEMT technologies. Logic gates with tens of picosecond delay, tens of microwatts of dissipated power together with wide operating temperature ranges and hardness to nuclear irradiation have been produced over the last few years. MSI and LSI levels of integration in GaAs have now been demonstrated most notably in the USA and Japan. The implementation of these circuits has placed severe controls on material and processing to allow high uniformity and yields to be achieved.
Mature Si bipolar and MOS technologies have demonstrated propagation delays of 300 to 400 picosecond with several milliwatts dissipation per gate (commercial ECL) and 200 to 300 pS delay with less than 1 mW per gate for laboratory n-MOS circuits. By decreasing device dimensions a 0.3 micron channel n-MOS circuit has achieved 30 pS gate delay at 1.7 mW/gate (Lepselter 1980) whilst a self aligned bipolar process achieved a 5.5 GHz divider result (Sakai, 1983). Recently a 9 GHz divider fabricated using a super self aligned bipolar technology (SST) with a transistor f T of 17...
