TABLE OF CONTENTS In order to give the reader an understanding of the relative complexity of GaAs integrated circuit manufacture when compared to discrete FET devices, the approaches being taken to define high yield processes are reviewed, Because many laboratories developing GaAs ICs have already considerable experience in the fabrication of discrete FETs there tends to be a marked resemblance between the two fabrication processes particularly where epitaxial layers are used.
To realize low noise and high gain FETs, the devices are optimized with respect to material parameters and device geometries as described in Chapter 2. Apart from the use of low resistance ohmic contacts usually utilizing AuGe/Ni, the FETs have multiple parallel gates for analogue applications to reduce gate resistance and as thick a gate metal as is possible. Photolithographic techniques are usually employed to define gate lengths down to 0.5 ?m. Below that value electron beam lithography is used using such equipment as the Cambridge EBMF2 (Lawes, 1979). Electron beam lithography is used for gate lengths greater than 0.5 ?m when a fast turn-around time is required (since no high definition gate mask is required) by directly exposing a resist using the electron beam. The electron beam machine automatically aligns the gates to alignment marks usually defined close to source and drain contacts which have been previously defined. Gate lengths of 0.2 ?m can be successfully defined.
In monolithic circuits device bonding pads generally do not occur as direct connection to the...
