TABLE OF CONTENTS An essential advantage of photonic integrated circuits based on 2DPC lies in their fabrication procedure which fits with the planar technological approach, familiar in the world of silicon microelectronics. Without sacrificing their generality, results presented as illustrations in the following sections concern essentially the cases of InP membranes either suspended in air or bonded onto silica on silicon substrate.
This latter technological approach opens up promising prospects for heterogeneous integration of optoelectronics devices based on III V compound semiconductors with silicon microelectronic circuits. The devices are designed for operation wavelengths of InP and related materials, that is in the 1.5 m range.
The heterostructure to be suspended is epitaxied on a semi-insulating InP substrate. It comprises a guiding InP layer with half-wavelength optical thickness (around 250nm) and may include active layers for emission or detection (for example InAsP quantum wells or InAs based quantum box layers), located at mid-height in the InP layer. The InP layer is formed on an InGaAs sacrificial layer, which is eliminated in order to suspend the former, leaving a quarter-wavelength air gap: the elimination of the sacrificial layer is achieved by applying a wet etch surface micromachining procedure. The thicknesses of the sacrificial layer and guiding layer are chosen so as to maximize the coupling of the active layer with fundamental TE waveguided mode (monomode operation) and to...
