TABLE OF CONTENTS The primary design goal for this LNA was to achieve an IIP 3 of +10 dBm, while consuming less than 10 mA of DC current. To this end, two techniques were employed: inductive emitter degeneration and the use of additional charge storage across the base-emitter junction of the transistor.
The usual method employed for measuring third-order intercept point (IP 3) involves injecting two equal amplitude sinusoidal signals at frequencies f 1 and f 2 into the amplifier input, and observing the relative levels of the test signals f 1, f 2 and third-order products 2f 2 ? f 1 and 2f 1 ? f 2 at the amplifier output. The third-order products, as well as all other signals present at the amplifier output besides f 1 and f 2, constitute distortion and are the result of nonlinear behavior within the transistor, most notably across the baseemitter junction. For the testing done on this particular LNA, each input test tone power level (PIN, input power for both f 1 and f 2) is set to ?20 dBm, and the spacing between the tones is nominally 1 MHz. The input thirdorder intercept point (IIP 3) is calculated as follows:
where ?IM 3 = the difference in amplitude between one of the two equal amplitude test tones present at the amplifier output and the level of the highest 3rd-order distortion product (see Figure 3).
