-
Supplier: MicroSense, LLC
Description: Throughput up to 100W/hours 2D & 3D mapping capability SECS/GEM communication. Automated calibration. Options Wafer prealigner HISCAN for Roughness and structures measurement Applications QA and QC of small size wafers, SiC, Sapphire, Glass, InP, etc…
- Applications: Semiconductor Wafers
- Form Factor: Monitor / Instrument
- Maximum Wafer / Part Size: 50 to 100 mm
- Measurement Capability: Thickness - Wafer / Disc (TTV)
-
Supplier: MTI Instruments Inc.
Description: . Wafer Specifications Diameter: 150 mm, 200 mm, 300 mm Material: All semiconducting and semi-insulating wafers including Si, GaAs, Ge, SiC, InP Surfaces: As-Cut, Lapped, Etched, Polished, Patterned Flat/Notch: All SEMI Standard Flat(s) or Notch Conductivity: P or N Type
- Applications: Semiconductor Wafers
- Area Mapping: Yes
- Form Factor: Wafer Probing System, Sensor / Sensing Element
- Maximum Wafer / Part Size: 300 mm
-
Supplier: Gelest, Inc.
Description: Safety Packaging Under None
- Inorganic Compounds: OrganoMetallics
-
-
Supplier: El-Cat, Inc.
Description: EL-CAT Inc. is a stocking distributor of Silicon Wafers, Compound Semiconductors and other Crystal Materials for use in electronics.
-
Supplier: Wolfspeed
Description: production line RF MMIC on-wafer probe / dice Microwave reliability labs RF applications support † Based on publicly available competitor data and customer feedback.
- Application: Aerospace / Defense, Fiber Optics / Telecommunications, Wireless
- Device Type: Specialty / Other
- Location: North America, United States Only, Southern US Only
- Logic Family: Indium Phosphide (InP), Other
-
Supplier: Universal Semiconductor, Inc.
Description: No Description Provided
- Application: Aerospace / Defense, Biotechnology / Medical, Automotive, Computer / PC, Fiber Optics / Telecommunications, Imaging / Vision, Wireless
- Device Type: Analog, ASIC , High Voltage, Logic, Memory, Passive Components, Sensors, Specialty / Other
- Device Voltage: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V
- Location: North America, United States Only, Southwest US Only
-
Supplier: Rogue Valley Microdevices, Inc.
Description: facility contains processing equipment capable of volume manufacturing yet flexible enough to accommodate wafer sizes from 50mm to 200mm. We offer full Device Fabrication and Design services along with a variety of individual processes to support our growing network of satisfied customers
- Application: Aerospace / Defense, Biotechnology / Medical, Automotive, Computer / PC, Fiber Optics / Telecommunications, Imaging / Vision, Wireless
- Device Type: Analog, ASIC , High Voltage, Logic, Memory, Microprocessor, Oscillator / Transistor-Oscillator (TO), Passive Components, Power Electronics, Sensors, Specialty / Other
- Device Voltage: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 5 V, Other
- Location: North America, United States Only, Northwest US Only
-
Supplier: HORIBA Instruments, Inc.
Description: is extremely stable and can be used with complex multi-layer films. Two types of lasers are available and compatible with a broad range of films including SiN, SiO2, GaAs, InP, AlGaAs, and GaN. This system consists of a compact interference measurement section that
-
Supplier: Marktech Optoelectronics
Description: the 1.0 um to 2.6um range, using InP material as the base substrate. Marktech is currently producing these high reliability wafers in 2", 3" and 4" diameters. Among the applications for these wafers are photo detectors, linear arrays and image sensors. Photo detectors processed
- Active Area Diameter or Length: 0.1000 mm
- PN, PIN, or Avalanche: PIN Photodiode
- Photodiode Material: Indium Gallium Arsenide
- Photodiode Package / Mounting: Other
![Real Time Interferometric Process Monitor [CCD] Laser Interference Camera -- LEM-CT-670-G50](https://partimages.globalspec.com/37/4787/5454787_medium.png "Real Time Interferometric Process Monitor [CCD] Laser Interference Camera -- LEM-CT-670-G50")
Find Suppliers by Category Top
More Information Top
Indicates content that may require registration and/or purchase.
-
Plasma-assisted InP-to-Si low temperature wafer bonding
However, the increment in wafer-size has not fol- lowed the same progress and there are major concerns about the upscaling of InP wafer dimensions [43].
-
http://dspace.mit.edu/bitstream/handle/1721.1/76119/821059170-MIT.pdf?sequence=2
is again deposited on the backside of the InP wafer .
-
Low temperature InP layer transfer onto Si by helium implantation and direct wafer bonding
The SOG coated InP wafers were subsequently bonded to thermally oxidized Si(1 0 0) handle wafers and the bonded wafer pairs were annealed at 200 ◦ C for 20 h to achieve InP layer transfer onto Si(1 0 0) wafers …
-
Long-wavelength (1.55-μm) vertical-cavity lasers with InGaAsP/InP-GaAs/AlAs DBR's by wafer fusion
Before wafer fusion, the GaAs wafer was slightly etched with buffered HF, and the InP wafers were etched with H SO : H O : H O (3 : 1 : 1) solution and buffered HF to remove native oxides.
-
http://dspace.mit.edu/bitstream/handle/1721.1/62448/711100539-MIT.pdf?sequence=2
After removing the photoresist, the iron doped InP-InGaAsP- InP wafer was etched for 2 minutes in a C12 / SiCl4 /Ar ICP RIE etch chemistry to obtain a uniform 2pm etch depth across the sample.
-
Springer Handbook of Crystal Growth
As re- cently as 2006, a new application for high-speed laser modulation was developed using 6 in InP wafers bonded to silicon [7.1].
-
Lapping Technique of InP Single Crystal Wafer
Still no results related to InP wafer lapping technique have been reported, even though there are some papers about InP polishing process and mechanism [ADACHI,KURTH,WEI].
-
EMERGING OPTOELECTRONIC TECHNOLOGIES AND APPLICATIONS
When bulk InP wafers were patterned, the etch depth was approximately 500 nm.
-
http://dspace.mit.edu/bitstream/handle/1721.1/44718/297547620-MIT.pdf?sequence=2
3-10 Schematic showing a (100) InP wafer and the associated cleavage planes 81 .
-
http://dspace.mit.edu/openaccess-disseminate/1721.1/54241
The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias.