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Supplier: Microchip Technology, Inc.
Description: This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock. Available
- Clock Frequency: 2000 MHz
- IC Package Type: Other
- Logic Family: Other
- Operating Current: 70 mA
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Supplier: Microchip Technology, Inc.
Description: This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a lower speed version of the input clock. Available
- Clock Frequency: 2000 MHz
- IC Package Type: Other
- Logic Family: Other
- Operating Current: 75 mA
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Supplier: Microchip Technology, Inc.
Description: The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create
- Clock Frequency: 2500 MHz
- IC Package Type: Other
- Logic Family: Other
- Operating Current: 50 mA
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Supplier: Microchip Technology, Inc.
Description: This low-skew, low-jitter device can accept a high-speed (622MHz or higher) LVTTL, LVCMOS, CML, LVPECL, LVDS or HSTL clock input signal and divide down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input
- Clock Frequency: 2500 MHz
- IC Package Type: Other
- Logic Family: Other
- Operating Current: 50 mA
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. The high-performance PLL has a -239 dBc/Hz for normalized in-band phase noise floor, ultra-low 1/f noise, and a high phase/frequency detector (PFD) frequency that can achieve ultra-low in-band noise and integrated jitter. The fundamental VCO and output divider of the ADF4378 generate frequencies (read more)
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Digital Electronics: Principles Devices and Applications Complete Document
… file 528, 529–30 buffer register 529–30 general purpose registers 529, 530 instruction register 529 program counter 529 stack pointer … … Repetition code 41 Resistive divider network 474–5 Resistor transistor logic , see RTL Resolution-A/D … … oscilloscope 674, 676–7 Resolution- frequency counter 682 Resolution-frequency … … Schmitt gates 88–91, 92 Schmitt trigger 358–60 Schmitt trigger-transfer characteristics 360 Schottky TTL 116, 124, 135–6 …
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A Frequency Synthesizer for Television Receivers
The purpose of the prescaler is to divide down the local oscil- lator high frequencies to a range that can be processed and counted by standard TTL logic . Output of the prescaler is then fed to the programmable divider which is the heart of the sys- tem.
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Highly accurate positioning control method for piezoelectric actuators based on phase-shifting optoelectronics
The frequency division ratios are obtained with logic divider Zarlink SP8400 components which are programmable from 16 to 8206 to obtain signals s1 and s2 both at a frequency of exactly 20 MHz. The inhibitions are done with a TTL command signal generated with direct digital synthesis (DDS) (DS345 Stanford …
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GaAs Fully Monolithic X Band SPDT Switch with Integrated TTL Compatible Driver
The TTL compatible logic driver interface was designed to generate complementary comnand signals for the switch. It includes 6 BFL gates with an electrostatic protection circuitry on the output line as used in high frequency dividers . The control circuit performance was analyzed using the time domain CAD program CIRCEC where a specific model …
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Pulse Research Lab Launches New Programmable TTL/NECL Frequency Divider
The input frequency f is first divided down to f/n, where 2 <= n=""><= 256 … … "" for="" the="" first-phase="" ecl="" and="" ttl ="" outputs="" and … … ratios="" are="" programmed ="" via="" a … The PRL-260ANT is for applications where a frequency divider or prescalar is needed for triggering or down-sampling, and the multiple logic inputs and outputs make it useful in mixed-logic environments.
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Pulse Research Lab Launches New Programmable TTL/NECL Frequency Divider
The input frequency f is first divided down to f/n, where 2 <= n=""><= 256 … … "" for="" the="" first-phase="" ecl="" and="" ttl ="" outputs="" and … … ratios="" are="" programmed ="" via="" a … The PRL-260ANT is for applications where a frequency divider or prescalar is needed for triggering or down-sampling, and the multiple logic inputs and outputs make it useful in mixed-logic environments.
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Electronics for engineers and natural scientists
… 462 Faraday effect 316 color coding 95 fiber-fiber-coupling 316 fiber-optic sensor 316 FAST (Fairchild-Advanced-Schottky TTL ) 446,448,454 code … … layer 194 -, controllable voltage divider 205 -, triode region 196 … … sensor 314 FF Toggle frequency 447 Ficksches law 66 … … 317 gate array 446, 521, 523 -, digital 540 -, channel 540 -, kanalloses 540, 539 -, programmable 540, 543 gate …
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A Medium-Cost PLL Varactor Tuning System Utilizing Off-The-Shelf Logic
The first three dividers are ECL high-speed, non-satu- rating logic which form a divide by 50. The number 50 was chosen so that the maximum divided input frequency would be in the range of standard TTL logic, 10 MHz or less. Two-cascaded Programmable Down Counters are used to divide by channel number thus giving a 120 kHz …
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Portable telephones for 850 MHz cellular systems
integer of the programmable counter and fl andf are two reference frequencies obtained respectively bya X3 multiplication and 8784 division ofa 43.29 MHz master crystal oscillator. Most of the frequency dividers employ TTL circuits since their incoming frequencies are in the multimegahertz region, thus the power consumption is quite high. C-MOS digital logic and swallow counting14is shown in Fig. 7.
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Military Logic Pricing and Availability
Programmable Logic Rate Multiplier/ Frequency Divider /Timer Backplane Logic (GTL/ TTL /BTL/ECL Transceiver/Translator .