3.9 Hardened processors

The concept of hardened processors has also been widely discussed. Rather than implementing a secure coprocessor, which runs in parallel to the general platform processor, the primary processor is extended such that certain applications can be run securely in on-chip protected compartments. A process running in one compartment has only strictly controlled access to application code or data from another compartment. Off-chip compartment application code and data is also protected through the deployment of encryption and integrity mechanisms.

We begin with a brief examination of the XOM architecture ^[34] which provides protected environments/compartments for XOM code to execute in. The XOM architecture essentially provides on-chip protection of caches and registers, protection of cache and register values during context switching and on interrupts and confidentiality and integrity protection of application code and data when transferred to external memory.

In order to implement practically and efficiently a XOM machine, extensive hardware additions must be made to the CPU. In a hardware implementation of the XOM machine, all trust is put in the modified CPU hardware. Everything transmitted outside the main CPU is encrypted.

On the other hand, however, the XOM virtual machine monitor (XVMM) Implementation of the XOM machine, described below, significantly reduces necessary CPU hardware extensions. A software XVMM, whose integrity is validated via secure boot, is used to provide an abundance of the security services provided directly by the CPU in the hardware implementation.

We subsequently explore the AEGIS architecture ^[35], which builds upon concepts...