TABLE OF CONTENTS This section presents a set of common inter-tasks synchronization and communication patterns designed from real-life scenarios. These design patterns are ready to be used in real-world embedded designs.
In these design patterns, the operation of event register manipulation is considered an atomic operation. The numberings shown in these design patterns indicate the execution orders.
Multiple ways of implementing synchronous activity synchronization are available, including:
task-to-task synchronization using binary semaphores,
ISR-to-task synchronization using binary semaphores,
task-to-task synchronization using event registers,
ISR-to-task synchronization using event registers,
ISR-to-task synchronization using counting semaphores, and
simple rendezvous with data passing.
In this design pattern, two tasks synchronize their activities using a binary semaphore, as shown in Figure 15.6. The initial value of the binary semaphore is 0. Task #2 has to wait for task #1 to reach an execution point, at which time, task #1 signals to task #2 its arrival at the execution point by giving the semaphore and changing the value of the binary semaphore to 1. At this point, depending on their execution priorities, task #2 can run if it has higher priority. The value of the binary semaphore is reset to 0 after the synchronization. In this design pattern, task #2 has execution dependency on task #1.
In this design pattern, a task and an ISR synchronize their activities using a binary...
