TABLE OF CONTENTS In this section, we discuss our leakage current model and briefly review the general characteristics of gate leakage current in CMOS gates.
Since the proposed leakage optimization approach is library-based, we use precharacterized leakage current tables for each library cell, with specific leakage table entries for each possible input state of a library cell. The precharacterized tables were constructed using SPICE simulation with BSIM3 models from 0.18 ?m technology for I sub minimization approach. In order to represent both I sub and I gate components for the state / V t / T ox assignment approach, BSIM4 models were used to generate the precharacterization of tables. The device simulation parameters were obtained using leakage estimates from a predicted 65nm processes [20], and had a gate leakage component that was approximately 36% of the total leakage at room temperature (at which all analysis is performed). [1] (Detailed numbers will be shown at Section 4.5.2.) Different high- and low- V t versions of a cell as well as T ox and V t versions of a cell will be explained further in Section 4.4.2. Also, the delay and output slope as a function of cell input slope and output loading were stored in precharacterized tables.
The total gate leakage for a library cell consists of several different components, depending on the input state of the gate, as illustrated for the inverter cell in Figure 4.1. The...
