Ultra Low-Power Electronics and Design

4.4: LEAKAGE REDUCTION METHOD FOR BOTH SUBTHRESHOLD AND GATE LEAKAGE CURRENT

4.4 LEAKAGE REDUCTION METHOD FOR BOTH SUBTHRESHOLD AND GATE LEAKAGE CURRENT

4.4.1 Leakage Reduction Approach

The proposed leakage optimization method performs simultaneous assignment of standby mode state and high- V t and thick-oxide transistors. The proposed method is based on the key observation that given a known input state, a transistor need not be assigned both a high- V t, and a thick oxide. This is due to the fact that if a transistor that is OFF, gate leakage is significantly reduced and hence the transistor only needs to be considered for high- V t assignment. Conversely, a transistor that, given a particular input state, is ON may exhibit significant I gate, but does not impact I sub. Hence, conducting transistors only need to be considered for thick oxide assignment. If the input state is unknown in standby mode, it cannot be predicted at design time which transistors will be ON or OFF and therefore all or most transistors must be assigned to both high- V t and thick-oxide in order to significantly reduce the total average leakage. However, given a known input state, we can avoid assignment of transistors to both high- V t and thick oxide, thereby significantly improving the obtained leakage / delay trade-off.

Furthermore, depending on the input state of a circuit, only a subset of transistors needs to be considered for high- V t or thick-oxide, as discussed in Section 4.3.1. For instance, in a stack of...

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