TABLE OF CONTENTS In this paper, we propose new approaches for standby leakage current minimization under delay constraints. Our approaches use simultaneous state assignment and V t or V t/ T ox assignment. Efficient methods for computing the simultaneous state and V t or V t/ T ox assignments leading to the minimum standby mode leakage current were presented. The proposed methods were implemented and tested on a set of synthesized benchmark circuits. Using the new state and V t assignment technique demonstrates 6X lower leakage than previous V t-only assignment approaches and 5X lower than state assignment alone (at 5% delay point). In cases where gate leakage is prominent, as in 90nm CMOS technologies, these improvements are increased by an additional factor of 2 using state and V t/ T ox assignment. We also investigate the leakage/complexity trade-off for various cell library configurations and demonstrate that results are still very good even when only 2 additional variants are used for each cell type.
The authors would like to thank Harmander Deogun for his work in leakage current model. The work has been supported by NSF, SRC, GSRC/DARPA, IBM, and Intel.
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