TABLE OF CONTENTS The proposed methods for simultaneous state and V t assignment were tested on the ISCAS benchmark circuits [27] and a 64-bit ALU circuit, synthesized using a 0.18 ?m industrial library with Synopsys. This technology has a difference of 14X (10X) in I sub and 16% (15%) in delay between low- V t and high- V t NMOS (PMOS) devices. The leakage current for each V t version of a cell was computed using SPICE simulation and stored in precharacterized tables. Delay computation was performed based on the Synopsys table delay model and was verified to match with Synopsys timing analysis delay reports. In addition to the proposed methods, traditional methods using only state or V t assignment were also implemented for comparison. The state-only assignment was implemented using the approach discussed in [25] while for V t-only assignment a method similar to the sensitivity-based approach of [17] was used.
Table 4.4 compares the leakage results obtained by the three proposed heuristics for three delay constraints to the average leakage computed using 10,000 random input vectors. The columns marked 0%, 5%, and 10% refer to leakage minimization results when the delay constraints were set at 0%, 5%, and 10% respectively, of the full delay range between all low- V t and all high- V t circuit delay, as illustrated in Figure 4.8. The 0% column is therefore the most stringently constrained optimization...
